﻿PAL timing cheat sheet for CPU at 6MHz:

 1cc = 1/6th µs.
 6cc =      1µs.
12cc =      2µs.
24cc =      4µs.
48cc =      8µs.

Total scanline:      64µs (384).
Half scanline:       32µs (192).
Display scanline:    4µs sync, 8µs black, 52µs picture. (24, 48, 312).
Vertical long sync:  30µs sync, 2µs black. (180, 12).
Vertical short sync: 2µs sync, 30µs black (12, 180).

Line   1: [Long vertical sync]  [Long vertical sync]
Line   2: [Long vertical sync]  [Long vertical sync]
Line   3: [Long vertical sync]  [Short vertical sync]
Line   4: [Short vertical sync] [Short vertical sync]
Line   5: [Short vertical sync] [Short vertical sync]
Line   6: [Picture]
Line  ..: ...
Line 309: [Picture]
Line 310: [Short vertical sync] [Short vertical sync]
Line 311: [Short vertical sync] [Short vertical sync]
Line 312: [Short vertical sync] [Short vertical sync]

Now, we can't output the vertical sync sequence entirely correctly, as the
6MHz clock speed is far too low to output 2µs pulses.

For vertical sync: total scanline = 384cc.
That is made up of four otirs = 4*16 = 64cc.
We must therefore waste 320cc in two halves of 160cc each.